A typical conventional CMOS imager circuit includes a focal plane array of pixel cells. Each cell includes a photo-conversion device such as, for example, a photogate, photoconductor, or photodiode, for generating and accumulating photo-generated charge in a portion of the substrate of the array. A readout circuit connected to each pixel cell includes at least an output transistor, which receives photo-generated charges from a doped diffusion region and produces an output signal that is read-out through a pixel access transistor.
One typical CMOS imager pixel circuit, the three-transistor (3T) pixel, contains a photo-conversion device for supplying photo-generated charge to a diffusion region; a reset transistor for resetting the diffusion region; a source follower transistor having a gate connected to the diffusion region, for producing an output signal; and a row select transistor for selectively connecting the source follower transistor to a column line of a pixel array. Three-transistor pixel cells have been used to support automatic light control (ALC) operations. ALC is used to control the amount of light integrated by a pixel cell. In a 3T pixel cell, the charge accumulated by a photo-conversion device may be read out prior to resetting the photo-conversion device to a predetermined voltage. Therefore, ALC operations may determine a time for readout based on the amount of charge generated by the photo-conversion device and may adjust the amount of charge further generated by the photo-conversion device in response to the charge present on the photo-conversion device at a particular time.
Another typical CMOS imager pixel employs a four-transistor (4T) configuration, which is similar to the 3T configuration, but utilizes a transfer transistor to gate charge carrier flow from the photo-conversion device to a sensing node, typically a floating diffusion region; in a 4T configuration, the source follower transistor gate is connected to the floating diffusion region.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the foregoing are hereby incorporated by reference herein in their entirety.
A schematic top view of a portion of a semiconductor wafer fragment containing one exemplary CMOS 4T pixel cell 100 is shown in FIG. 1. CMOS pixel cell 100 generally comprises a photo-conversion device 120 for generating charge in response to external light incident on the pixel, and a transfer gate 106 for transferring photoelectric charges from the device 120 to a sensing node, typically a floating diffusion region 110. The floating diffusion region 110 is electrically connected to the gate 108 of an output source follower transistor. The pixel cell 100 also includes a reset transistor having a gate 107 for resetting the floating diffusion region 110 to a predetermined voltage before sensing a signal; and a row select transistor having a gate 109 for outputting a signal from the source follower transistor to an output terminal in response to a row select signal. There are also source/drain regions 115 for the reset, source follower, and row select transistors.
FIG. 2 is a diagrammatic side sectional view of the pixel cell 100 of FIG. 1 taken along line 2–2′. As shown in FIG. 2, the exemplary CMOS pixel cell 100 has a pinned photodiode as the photo-conversion device 120. Pinned photodiode 120 is adjacent to the gate 106 of a transfer transistor and has a p-n-p construction comprising a p-type surface layer 123 and an n-type photodiode region 122 within a p-type substrate 101.
In the CMOS pixel cell 100 depicted in FIGS. 1 and 2, free electrons are generated by incident light and accumulate in the n-type photodiode region 122. This photo-generated charge is transferred to the floating diffusion region 110 when gate 106 receives a signal that turns on the transfer transistor. The source follower transistor produces an output signal from the transferred charge in response to the voltage level received by gate 108.
Typically, as shown in FIG. 2, pinned photodiode 120 is exposed to external light, represented by arrows 187. Other portions of pixel cell 100 are shielded from light, for example, by a metal layer 186. Structures formed above pinned photodiode 120 are typically transparent and may include a color filter 185 and a microlens 180. Conventional pixel cell 100 may also include other layers formed over substrate 101 and photodiode 120, such as insulating and passivation layers (not shown).
The 4T configuration of FIGS. 1 and 2 provides advantages over the 3T configuration. For example, pixel cell 100 is capable of supporting correlated double sampling (CDS) to reduce noise and obtain a more accurate pixel signal. For CDS, the predetermined voltage to which floating diffusion region 110 controls gate 108 to read out a pixel reset signal Vrst. Then, photo-generated charge from pinned photodiode 120 is transferred to floating diffusion region 110 by operation of transfer gate 106 and a pixel image signal, Vpc1, is read out via the source follower gate 108. The two values, Vrst, and Vpc1, are subtracted thereby reducing noise. Additionally, 4T pixel cell 100 provides lower dark current, which also reduces noise. Accordingly, in a conventional pixel cell 100, because the transfer gate 106 gates the flow of photo-generated charge from the pinned photodiode 120 to the floating diffusion region 110 and, therefore, to readout circuitry, it is not possible to read out photo-generated charge without altering the charge on pinned photodiode 120. Therefore, ALC is not readily used with a conventional 4T pixel cell.
It would be advantageous to have improved techniques for measuring pixel light levels, particularly for 4T pixel cells and other pixel cell having greater than four transistors.